The present invention relates to a data processor including CPU (Central Processing Unit), and to a technique useful in application to e.g. a microprocessor.
In regard to a microprocessor—an example of a data processor, it is sometimes required for software program to execute a process of making reference to a table. In an application, e.g. a process of image coding, reference is made to a table during a variable codeword length coding, etc. In such case, the process of making reference to a table is realized by a procedure which includes mapping a reference table onto a data memory, and making the index and data referred by the index at the table corresponding to the address and the word value of the data memory, respectively. In the process like this, a special processing is sometimes conducted depending on data resulting from the table reference further. In the case of image coding, examples of the special processing are ESCAPE in a RUN/LEVEL decode process in MPEG-2 (ISO/IEC 13818) or the like, and an error processing in response to error detection during a decode process of video streams. For such special processing, the following steps are taken, for example: setting a certain value for comparison to data of the result of table reference or asserting a certain bit field; and checking data of the result of table reference and selectively branching to the special processing according to a conditional branch instruction. Japanese Unexamined Patent Publication No. JP-A-2006-313561 discloses a data processor, such as a microprocessor, which actually performs a process as described above by use of a combination of two or more instructions. Such data processor executes a group of steps of reading data and checking the read data, to the step of branching using a prefix instruction which makes a combining of a data transfer instruction and a bit conditional branch instruction, as if the group of steps is one process executed in response to one instruction.